OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.1rc1/] [peripheral/] [eth.c] - Rev 840

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
511 Tagging the 0.5.1rc1 release of Or1ksim jeremybennett 4829d 17h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c
508 Updates for Or1ksim 0.5.0rc3. jeremybennett 4830d 17h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 4922d 18h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4932d 12h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c
451 More tidying up. jeremybennett 4943d 08h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 4943d 12h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c
443 Work in progress on more efficient Ethernet. jeremybennett 4948d 16h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4949d 07h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c
437 Or1ksim - ethernet peripheral update, working much better. julius 4958d 03h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 4959d 03h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 4962d 09h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c
429 or1ksim update - remove debug printfs from eth MDIO emulation function
and fix illegal instruction vector jump for invalid instructions.
julius 4966d 12h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 4969d 08h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5081d 17h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.
jeremybennett 5182d 09h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5512d 19h /openrisc/tags/or1ksim/or1ksim-0.5.1rc1/peripheral/eth.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.