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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Rev 816

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804 OR1200: Fix for bug 91

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91		 julius 4567d 16h /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
802 OR1200: Fix for bug 88

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88		 julius 4572d 22h /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
788 or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 julius 4630d 21h /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
674 or1200: Fix for Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled julius 4697d 06h /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
643 or1200: new ALU comparision implementation option, TLB invalidate register indicated as not present, multiply overflow detection bug fix julius 4835d 21h /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
642 or1200: add carry, overflow bits, and range exception julius 4835d 21h /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
640 or1200: add l.ext instructions, fix a MAC bug julius 4835d 21h /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
481 OR1200 Update. RTL and spec. julius 5061d 13h /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
401 Fixing find first one (ff1) and find last one (fl1) support in OR1200.

Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported
instructions table.		 julius 5140d 01h /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 5189d 22h /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5202d 16h /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5253d 00h /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
141 added OpenRISC version rel3 marcus.erlandsson 5264d 04h /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
10 or1200 added from or1k subversion repository unneback 5665d 07h /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v

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