URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_cfgr.v] - Rev 339

Rev	Log message	Author	Age	Path
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5200d 20h	/openrisc/trunk/or1200/rtl/verilog/or1200_cfgr.v
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5251d 04h	/openrisc/trunk/or1200/rtl/verilog/or1200_cfgr.v
141	added OpenRISC version rel3	marcus.erlandsson	5262d 08h	/openrisc/trunk/or1200/rtl/verilog/or1200_cfgr.v
10	or1200 added from or1k subversion repository	unneback	5663d 12h	/openrisc/trunk/or1200/rtl/verilog/or1200_cfgr.v