URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Rev 405

Rev	Log message	Author	Age	Path
401	Fixing find first one (ff1) and find last one (fl1) support in OR1200. Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported instructions table.	julius	5230d 07h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5292d 22h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
186	OR1200 RTL FPU fix - RF writeback signal working properly again	julius	5343d 05h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5343d 06h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
141	added OpenRISC version rel3	marcus.erlandsson	5354d 10h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
10	or1200 added from or1k subversion repository	unneback	5755d 13h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v