URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Rev 466

Rev	Log message	Author	Age	Path
401	Fixing find first one (ff1) and find last one (fl1) support in OR1200. Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported instructions table.	julius	5045d 21h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5108d 12h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
186	OR1200 RTL FPU fix - RF writeback signal working properly again	julius	5158d 19h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5158d 20h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
141	added OpenRISC version rel3	marcus.erlandsson	5170d 00h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
10	or1200 added from or1k subversion repository	unneback	5571d 04h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v