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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Rev 588

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Rev Log message Author Age Path
481 OR1200 Update. RTL and spec. julius 5089d 09h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
401 Fixing find first one (ff1) and find last one (fl1) support in OR1200.

Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported
instructions table.
julius 5167d 22h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5230d 12h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
186 OR1200 RTL FPU fix - RF writeback signal working properly again julius 5280d 20h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5280d 20h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
141 added OpenRISC version rel3 marcus.erlandsson 5292d 00h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
10 or1200 added from or1k subversion repository unneback 5693d 04h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v

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