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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Rev 852

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847 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>		 stekern 4445d 09h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
813 or1200: Set correct PC after reset when parameter boot_adr is used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 olof 4480d 20h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
808 OR1200: Add DSX bit support to SR.

Updated documentation, revision is now 13.

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85		 julius 4596d 13h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
642 or1200: add carry, overflow bits, and range exception julius 4864d 18h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
640 or1200: add l.ext instructions, fix a MAC bug julius 4864d 18h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
481 OR1200 Update. RTL and spec. julius 5090d 10h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
401 Fixing find first one (ff1) and find last one (fl1) support in OR1200.

Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported
instructions table.		 julius 5168d 22h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5231d 13h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
186 OR1200 RTL FPU fix - RF writeback signal working properly again julius 5281d 20h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5281d 21h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
141 added OpenRISC version rel3 marcus.erlandsson 5293d 01h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
10 or1200 added from or1k subversion repository unneback 5694d 05h /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v

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