OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 356

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
259 Fixing or1200_defines FPU module selection defines - They are no longer needed julius 5039d 17h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5039d 18h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5090d 02h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
141 added OpenRISC version rel3 marcus.erlandsson 5101d 06h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
10 or1200 added from or1k subversion repository unneback 5502d 09h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.