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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 841

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813 or1200: Set correct PC after reset when parameter boot_adr is used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 olof 4430d 01h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
808 OR1200: Add DSX bit support to SR.

Updated documentation, revision is now 13.

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85		 julius 4545d 19h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
643 or1200: new ALU comparision implementation option, TLB invalidate register indicated as not present, multiply overflow detection bug fix julius 4813d 23h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
642 or1200: add carry, overflow bits, and range exception julius 4813d 23h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
640 or1200: add l.ext instructions, fix a MAC bug julius 4813d 23h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
481 OR1200 Update. RTL and spec. julius 5039d 15h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
401 Fixing find first one (ff1) and find last one (fl1) support in OR1200.

Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported
instructions table.		 julius 5118d 04h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 5168d 00h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5170d 09h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
259 Fixing or1200_defines FPU module selection defines - They are no longer needed julius 5180d 18h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5180d 19h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5231d 03h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
141 added OpenRISC version rel3 marcus.erlandsson 5242d 07h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
10 or1200 added from or1k subversion repository unneback 5643d 10h /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v

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