OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dpram.v] - Rev 830

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
639 or1200: or1200_dpram.v change task set_gpr to function julius 4819d 18h /openrisc/trunk/or1200/rtl/verilog/or1200_dpram.v
481 OR1200 Update. RTL and spec. julius 5045d 10h /openrisc/trunk/or1200/rtl/verilog/or1200_dpram.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5186d 13h /openrisc/trunk/or1200/rtl/verilog/or1200_dpram.v
151 OR1200 rel3 (added some files that were not checked-in earlier) marcus.erlandsson 5245d 17h /openrisc/trunk/or1200/rtl/verilog/or1200_dpram.v
142 added OpenRISC version rel3 marcus.erlandsson 5248d 01h /openrisc/trunk/or1200/rtl/verilog/or1200_dpram.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.