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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_du.v] - Rev 822

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815 OR1200 debug unit: prevent deadlock when trap instruction stalls

As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.

The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result.		 yannv 4419d 14h /openrisc/trunk/or1200/rtl/verilog/or1200_du.v
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 5172d 06h /openrisc/trunk/or1200/rtl/verilog/or1200_du.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5174d 15h /openrisc/trunk/or1200/rtl/verilog/or1200_du.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5185d 00h /openrisc/trunk/or1200/rtl/verilog/or1200_du.v
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5235d 08h /openrisc/trunk/or1200/rtl/verilog/or1200_du.v
141 added OpenRISC version rel3 marcus.erlandsson 5246d 12h /openrisc/trunk/or1200/rtl/verilog/or1200_du.v
10 or1200 added from or1k subversion repository unneback 5647d 16h /openrisc/trunk/or1200/rtl/verilog/or1200_du.v

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