URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_fpu.v] - Rev 346

Rev	Log message	Author	Age	Path
260	Fixed `define in FPU that didnt need to be there	julius	5176d 18h	/openrisc/trunk/or1200/rtl/verilog/or1200_fpu.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5178d 14h	/openrisc/trunk/or1200/rtl/verilog/or1200_fpu.v
186	OR1200 RTL FPU fix - RF writeback signal working properly again	julius	5228d 21h	/openrisc/trunk/or1200/rtl/verilog/or1200_fpu.v
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5228d 22h	/openrisc/trunk/or1200/rtl/verilog/or1200_fpu.v