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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Rev 851

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847 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>		 stekern 4421d 14h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
813 or1200: Set correct PC after reset when parameter boot_adr is used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 olof 4457d 01h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 5195d 00h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5197d 09h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5207d 18h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
186 OR1200 RTL FPU fix - RF writeback signal working properly again julius 5258d 01h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
141 added OpenRISC version rel3 marcus.erlandsson 5269d 06h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
10 or1200 added from or1k subversion repository unneback 5670d 10h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v

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