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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ic_fsm.v] - Rev 846

Rev	Log message	Author	Age	Path
846	or1200: Fix for cache bug related to first_{hit\|miss}_ack Under certain circumstances, when first_hit_ack and first_miss_ack is asserted at the same time, cache data would wrongly be overwritten with bus data. Patch by: Matthew Hicks <firefalcon@gmail.com>	stekern	4412d 14h	/openrisc/trunk/or1200/rtl/verilog/or1200_ic_fsm.v
481	OR1200 Update. RTL and spec.	julius	5057d 15h	/openrisc/trunk/or1200/rtl/verilog/or1200_ic_fsm.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5188d 09h	/openrisc/trunk/or1200/rtl/verilog/or1200_ic_fsm.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5198d 18h	/openrisc/trunk/or1200/rtl/verilog/or1200_ic_fsm.v
141	added OpenRISC version rel3	marcus.erlandsson	5260d 06h	/openrisc/trunk/or1200/rtl/verilog/or1200_ic_fsm.v
10	or1200 added from or1k subversion repository	unneback	5661d 10h	/openrisc/trunk/or1200/rtl/verilog/or1200_ic_fsm.v