URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ic_top.v] - Rev 486

Rev	Log message	Author	Age	Path
481	OR1200 Update. RTL and spec.	julius	5088d 15h	/openrisc/trunk/or1200/rtl/verilog/or1200_ic_top.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5229d 18h	/openrisc/trunk/or1200/rtl/verilog/or1200_ic_top.v
141	added OpenRISC version rel3	marcus.erlandsson	5291d 06h	/openrisc/trunk/or1200/rtl/verilog/or1200_ic_top.v
10	or1200 added from or1k subversion repository	unneback	5692d 10h	/openrisc/trunk/or1200/rtl/verilog/or1200_ic_top.v