OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_immu_top.v] - Rev 680

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
679 Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
olof 4633d 14h /openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v
481 OR1200 Update. RTL and spec. julius 5040d 05h /openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.
julius 5170d 23h /openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5181d 09h /openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v
141 added OpenRISC version rel3 marcus.erlandsson 5242d 21h /openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v
10 or1200 added from or1k subversion repository unneback 5644d 00h /openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.