OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_mult_mac.v] - Rev 797

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
644 or1200: the infamous l.rfe fix, and bug fix for when multiply is disabled julius 4867d 03h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
643 or1200: new ALU comparision implementation option, TLB invalidate register indicated as not present, multiply overflow detection bug fix julius 4867d 03h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
642 or1200: add carry, overflow bits, and range exception julius 4867d 03h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
641 or1200: fix serial multiply/divide bug julius 4867d 03h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
640 or1200: add l.ext instructions, fix a MAC bug julius 4867d 03h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
481 OR1200 Update. RTL and spec. julius 5092d 19h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 5221d 04h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5223d 13h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests		 julius 5223d 22h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5233d 22h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
141 added OpenRISC version rel3 marcus.erlandsson 5295d 11h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
10 or1200 added from or1k subversion repository unneback 5696d 14h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.