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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_128x32.v] - Rev 441

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358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.
julius 5206d 18h /openrisc/trunk/or1200/rtl/verilog/or1200_spram_128x32.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5217d 03h /openrisc/trunk/or1200/rtl/verilog/or1200_spram_128x32.v
142 added OpenRISC version rel3 marcus.erlandsson 5278d 15h /openrisc/trunk/or1200/rtl/verilog/or1200_spram_128x32.v
10 or1200 added from or1k subversion repository unneback 5679d 19h /openrisc/trunk/or1200/rtl/verilog/or1200_spram_128x32.v

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