OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x14.v] - Rev 852

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.
julius 5221d 04h /openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x14.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5231d 13h /openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x14.v
142 added OpenRISC version rel3 marcus.erlandsson 5293d 01h /openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x14.v
10 or1200 added from or1k subversion repository unneback 5694d 05h /openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x14.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.