URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Rev 270

Rev	Log message	Author	Age	Path
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5217d 21h	/openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v
187	Or1200 sprs FPU update	julius	5268d 01h	/openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v
186	OR1200 RTL FPU fix - RF writeback signal working properly again	julius	5268d 04h	/openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5268d 05h	/openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v
151	OR1200 rel3 (added some files that were not checked-in earlier)	marcus.erlandsson	5277d 01h	/openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v
142	added OpenRISC version rel3	marcus.erlandsson	5279d 09h	/openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v
10	or1200 added from or1k subversion repository	unneback	5680d 12h	/openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v