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[/] [openrisc/] [trunk/] [or1ksim/] [ChangeLog] - Rev 194

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143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5265d 06h /openrisc/trunk/or1ksim/ChangeLog
134 Updates for stable release 0.4.0 jeremybennett 5273d 09h /openrisc/trunk/or1ksim/ChangeLog
127 New config option to allow l.xori with unsigned operand. jeremybennett 5279d 06h /openrisc/trunk/or1ksim/ChangeLog
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5280d 01h /openrisc/trunk/or1ksim/ChangeLog
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5280d 05h /openrisc/trunk/or1ksim/ChangeLog
122 Added l.ror and l.rori with associated tests. jeremybennett 5281d 01h /openrisc/trunk/or1ksim/ChangeLog
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5281d 02h /openrisc/trunk/or1ksim/ChangeLog
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5281d 23h /openrisc/trunk/or1ksim/ChangeLog
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5284d 02h /openrisc/trunk/or1ksim/ChangeLog
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5285d 02h /openrisc/trunk/or1ksim/ChangeLog
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5285d 03h /openrisc/trunk/or1ksim/ChangeLog
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5286d 02h /openrisc/trunk/or1ksim/ChangeLog
110 or1ksim make check should work without a libc in the or32-elf tools julius 5287d 03h /openrisc/trunk/or1ksim/ChangeLog
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5289d 02h /openrisc/trunk/or1ksim/ChangeLog
104 Candidate release 0.4.0rc4 jeremybennett 5292d 10h /openrisc/trunk/or1ksim/ChangeLog
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5301d 04h /openrisc/trunk/or1ksim/ChangeLog
99 Bug in test evaluation for library fixed. jeremybennett 5306d 04h /openrisc/trunk/or1ksim/ChangeLog
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5307d 05h /openrisc/trunk/or1ksim/ChangeLog
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5321d 11h /openrisc/trunk/or1ksim/ChangeLog
96 Various changes which had not been picked up in earlier commits. jeremybennett 5322d 12h /openrisc/trunk/or1ksim/ChangeLog

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