OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [ChangeLog] - Rev 212

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
202 Adding executed log in binary format capability to or1ksim julius 5229d 03h /openrisc/trunk/or1ksim/ChangeLog
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5246d 04h /openrisc/trunk/or1ksim/ChangeLog
134 Updates for stable release 0.4.0 jeremybennett 5254d 08h /openrisc/trunk/or1ksim/ChangeLog
127 New config option to allow l.xori with unsigned operand. jeremybennett 5260d 04h /openrisc/trunk/or1ksim/ChangeLog
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5261d 00h /openrisc/trunk/or1ksim/ChangeLog
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5261d 04h /openrisc/trunk/or1ksim/ChangeLog
122 Added l.ror and l.rori with associated tests. jeremybennett 5262d 00h /openrisc/trunk/or1ksim/ChangeLog
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5262d 00h /openrisc/trunk/or1ksim/ChangeLog
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5262d 21h /openrisc/trunk/or1ksim/ChangeLog
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5265d 00h /openrisc/trunk/or1ksim/ChangeLog
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5266d 00h /openrisc/trunk/or1ksim/ChangeLog
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5266d 01h /openrisc/trunk/or1ksim/ChangeLog
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5267d 00h /openrisc/trunk/or1ksim/ChangeLog
110 or1ksim make check should work without a libc in the or32-elf tools julius 5268d 01h /openrisc/trunk/or1ksim/ChangeLog
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5270d 01h /openrisc/trunk/or1ksim/ChangeLog
104 Candidate release 0.4.0rc4 jeremybennett 5273d 08h /openrisc/trunk/or1ksim/ChangeLog
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5282d 02h /openrisc/trunk/or1ksim/ChangeLog
99 Bug in test evaluation for library fixed. jeremybennett 5287d 02h /openrisc/trunk/or1ksim/ChangeLog
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5288d 03h /openrisc/trunk/or1ksim/ChangeLog
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5302d 09h /openrisc/trunk/or1ksim/ChangeLog

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.