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[/] [openrisc/] [trunk/] [or1ksim/] [ChangeLog] - Rev 404

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387 Fixed testing, to always use our DEJAGNU config. jeremybennett 5158d 20h /openrisc/trunk/or1ksim/ChangeLog
385 Updates for Or1ksim 0.5.0rc2.

* configure: Regenerated.
* configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.

* testsuite/test-code-or1k/configure: Regenerated.
* testsuite/test-code-or1k/configure.ac: Handle the case where
target_cpu is not set. Version changed to 0.5.0rc2.
* testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
Definition corrected.
jeremybennett 5158d 21h /openrisc/trunk/or1ksim/ChangeLog
376 Adding handling cases for RSP queries seen from new gdb-7.2 in RSP servers in
or1ksim and or_debug_proxy.

Adding ChangeLog to or_debug_proxy
julius 5166d 03h /openrisc/trunk/or1ksim/ChangeLog
346 Changes to support Or1ksim 0.5.0rc1

Top level changes:

* config.h.in: Regenerated.
* debug.cfg, rsp.cfg: Deleted.
* doc/or1ksim.texi: Updated for new options and library interface.
* doc/or1ksim.info, doc/version.texi: Regenerated.
* Makefile.am: Added sim.cfg to EXTRA_DIST.
* NEWS: Updated for 0.5.0rc1.
* or1ksim.h <enum or1ksim_rc>: OR1KSIM_RC_OK explicitly zero.
* sim.cfg: Updated for consistency with the user guide.
* sim-config.c (init_defconfig): 50000 as default VAPI port.
(alloc_memory_block): Verbose message of amount allocated.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.

Changes in testsuite:

* libsim.tests/int-edge.exp <int-edge simple 1>: Increase time
between interrupts to 2ms.
<int-edge simple 2>: Increase time between interrupts to 2ms.
<int-edge duplicated 1>: Increase time between interrupts to 2ms.
<int-edge duplicated 2>: Increase time between interrupts to 2ms.

Changes in testsuite/test-code-or1k:

* mc-common/except-mc.S: Remove leading underscores from global
symbols.
* except/except.S: Remove leading underscores from global symbols.
* cache/cache-asm.S: Remove leading underscores from global symbols.
* cache/cache.c (jump_and_link): Remove leading underscore from
label.
(jump): Remove leading underscore from label.
(all): Remove leading underscore from global symbol references.
* testfloat/systfloat.S: Remove leading underscores from global
symbols.
* mmu/mmu.c (jump): Remove leading underscore from label.
* mmu/mmu-asm.S: Remove leading underscores from global symbols.
* except-test/except-test.c: Remove leading underscores from
global symbols.
* except-test/except-test-s.S: Remove leading underscores from
global symbols.
* uos/except-or32.S: Remove leading underscores from global
symbols.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.
jeremybennett 5184d 00h /openrisc/trunk/or1ksim/ChangeLog
240 or1ksim build fixups for Cygwin copilation julius 5214d 02h /openrisc/trunk/or1ksim/ChangeLog
239 or1ksim fixed SPR_VR_RESV value julius 5215d 22h /openrisc/trunk/or1ksim/ChangeLog
236 Terminate execution on NOP_EXIT, even if debugging, add support for RSP qAttached packet, stall in library after single instruction is ST bit is set in SPR DMR1. Fix softfloat to allow compilation with -O0 for debugging.

* configure: Regenerated.
* configure.ac: Version changed to current date. Test for
varargs.h dropped.
* cpu/or32/insnset.c <l_nop>: Terminate execution on NOP_EXIT,
even if debugging.
* debug/rsp-server.c (rsp_query): Added support for qAttached
packet.
* libtoplevel.c (or1ksim_run): Stall after a single instruction if
SPR_DMR1_ST flag is set.
* softfloat/host.h: Make #define of INLINE conditional, to allow
the user to override.
* softfloat/README: Added instructions for non-optimized compilation.
* softfloat/softfloat-macros: Add a conditional #ifndef
NO_SOFTFLOAT_UNUSUED around unused functions.
jeremybennett 5217d 19h /openrisc/trunk/or1ksim/ChangeLog
235 Removed support for old OpenRISC JTAG Remote Protocol. jeremybennett 5218d 00h /openrisc/trunk/or1ksim/ChangeLog
234 Minor tidy ups. DOS end of line chars fixed. jeremybennett 5219d 01h /openrisc/trunk/or1ksim/ChangeLog
233 New softfloat FPU and testfloat sw for or1ksim julius 5219d 12h /openrisc/trunk/or1ksim/ChangeLog
230 Changed library interface. Fixed namespace problems with instruction lookup in library.

* configure: Regenerated.
* configure.ac: Version changed to current date.
* cpu/or1k/opcode/or32.h <or1ksim_build_automata>: Renamed from
build_automata.
<l_none, num_opcodes, insn_index>: Deleted.
<or1ksim_op_start>: Renamed from op_start.
<or1ksim_automata>: Renamed from automata.
<or1ksim_ti>: Renamed from ti.
<or1ksim_or32_opcodes>: Renamed from or32_opcodes.
<or1ksim_disassembled>: Renamed from disassembled.
<or1ksim_insn_len>: Renamed from insn_len.
<or1ksim_insn_name>: Renamed from insn_name.
<or1ksim_destruct_automata>: Renamed from destruct_automata.
<or1ksim_insn_decode>: Renamed from insn_decode.
<or1ksim_disassemble_insn>: Renamed from disassemble_insn.
<or1ksim_disassemble_index>: Renamed from disassemble_index.
<or1ksim_extend_imm>: Renamed from extend_imm.
<or1ksim_or32_extract>: Renamed from or32_extract
* cpu/or32/or32.c, cpu/or32/execute.c, cpu/or32/generate.c,
* cpu/common/stats.c, cpu/common/abstract.c, cpu/common/parse.c,
* cpu/or1k/opcode/or32.h, cuc/load.c, cuc/cuc.c,
* support/dumpverilog.c, toplevel-support.c: Renaming
corresponding to changes in cpu/or1k/opcode/or32.h.
* cpu/or32/execute-fp.h: Deleted
* cpu/or32/generate.c <include_strings>: Remove reference to
execute-fp.h
* cpu/or32/execute.c <host_fp_rm>: Declared static.
(fp_set_flags_restore_host_rm, fp_set_or1k_rm): Declared static,
forward declaration removed.
* or1ksim.h (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int.
* libtoplevel.c (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int.
jeremybennett 5220d 17h /openrisc/trunk/or1ksim/ChangeLog
226 Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated julius 5222d 17h /openrisc/trunk/or1ksim/ChangeLog
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5223d 01h /openrisc/trunk/or1ksim/ChangeLog
220 Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this. jeremybennett 5229d 16h /openrisc/trunk/or1ksim/ChangeLog
202 Adding executed log in binary format capability to or1ksim julius 5235d 20h /openrisc/trunk/or1ksim/ChangeLog
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5252d 21h /openrisc/trunk/or1ksim/ChangeLog
134 Updates for stable release 0.4.0 jeremybennett 5261d 01h /openrisc/trunk/or1ksim/ChangeLog
127 New config option to allow l.xori with unsigned operand. jeremybennett 5266d 21h /openrisc/trunk/or1ksim/ChangeLog
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5267d 17h /openrisc/trunk/or1ksim/ChangeLog
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5267d 21h /openrisc/trunk/or1ksim/ChangeLog

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