OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [NEWS] - Rev 241

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5219d 07h /openrisc/trunk/or1ksim/NEWS
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5249d 04h /openrisc/trunk/or1ksim/NEWS
134 Updates for stable release 0.4.0 jeremybennett 5257d 07h /openrisc/trunk/or1ksim/NEWS
127 New config option to allow l.xori with unsigned operand. jeremybennett 5263d 04h /openrisc/trunk/or1ksim/NEWS
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5263d 23h /openrisc/trunk/or1ksim/NEWS
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5264d 03h /openrisc/trunk/or1ksim/NEWS
122 Added l.ror and l.rori with associated tests. jeremybennett 5264d 23h /openrisc/trunk/or1ksim/NEWS
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5265d 00h /openrisc/trunk/or1ksim/NEWS
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5265d 21h /openrisc/trunk/or1ksim/NEWS
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5268d 00h /openrisc/trunk/or1ksim/NEWS
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5269d 00h /openrisc/trunk/or1ksim/NEWS
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5269d 01h /openrisc/trunk/or1ksim/NEWS
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5273d 00h /openrisc/trunk/or1ksim/NEWS
104 Candidate release 0.4.0rc4 jeremybennett 5276d 08h /openrisc/trunk/or1ksim/NEWS
89 Tidy up for latest bug fixes. jeremybennett 5319d 07h /openrisc/trunk/or1ksim/NEWS
88 Fix to bug 1710. jeremybennett 5319d 08h /openrisc/trunk/or1ksim/NEWS
86 Bug 1723 fixed (PS2 keyboard error message clarification). jeremybennett 5319d 08h /openrisc/trunk/or1ksim/NEWS
85 Bug 1773 (RSP usage with ELF image preloaded) fixed. jeremybennett 5319d 09h /openrisc/trunk/or1ksim/NEWS
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5650d 09h /openrisc/trunk/or1ksim/NEWS

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.