URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [autom4te.cache/] [output.0] - Rev 454

Rev	Log message	Author	Age	Path
442	OR1Ksim - adding trace controlability by SIGUSR1 signal.	julius	5080d 07h	/openrisc/trunk/or1ksim/autom4te.cache/output.0
436	Or1ksim ethernet TAP updates. Ethernet test still failing.	julius	5090d 03h	/openrisc/trunk/or1ksim/autom4te.cache/output.0
428	or1ksim - adding preliminary PHY emulation to ethernet peripheral.	julius	5100d 08h	/openrisc/trunk/or1ksim/autom4te.cache/output.0
418	Or1ksim - adding new option when configuring memories, "exitnops"	julius	5108d 16h	/openrisc/trunk/or1ksim/autom4te.cache/output.0
233	New softfloat FPU and testfloat sw for or1ksim	julius	5209d 04h	/openrisc/trunk/or1ksim/autom4te.cache/output.0
226	Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated	julius	5212d 10h	/openrisc/trunk/or1ksim/autom4te.cache/output.0
202	Adding executed log in binary format capability to or1ksim	julius	5225d 13h	/openrisc/trunk/or1ksim/autom4te.cache/output.0
60	Mark Jarvin's patches to support Mac OS X (Snow Leopard).	jeremybennett	5431d 12h	/openrisc/trunk/or1ksim/autom4te.cache/output.0
19	Initial commit of Or1ksim 0.3.0 into the new repository	jeremybennett	5643d 19h	/openrisc/trunk/or1ksim/autom4te.cache/output.0