OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [autom4te.cache/] [output.1] - Rev 686

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
556 or1ksim - added performance counters unit and test for it. julius 4919d 23h /openrisc/trunk/or1ksim/autom4te.cache/output.1
552 or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets julius 4921d 07h /openrisc/trunk/or1ksim/autom4te.cache/output.1
538 or1ksim updates. spr-def.h updates, Cygwin compile error fixes. julius 4948d 03h /openrisc/trunk/or1ksim/autom4te.cache/output.1
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 5082d 02h /openrisc/trunk/or1ksim/autom4te.cache/output.1
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 5108d 17h /openrisc/trunk/or1ksim/autom4te.cache/output.1
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 5118d 22h /openrisc/trunk/or1ksim/autom4te.cache/output.1
233 New softfloat FPU and testfloat sw for or1ksim julius 5227d 19h /openrisc/trunk/or1ksim/autom4te.cache/output.1
226 Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated julius 5231d 00h /openrisc/trunk/or1ksim/autom4te.cache/output.1
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5450d 02h /openrisc/trunk/or1ksim/autom4te.cache/output.1
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5662d 09h /openrisc/trunk/or1ksim/autom4te.cache/output.1

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.