OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [autom4te.cache/] [requests] - Rev 822

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
552 or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets julius 4911d 08h /openrisc/trunk/or1ksim/autom4te.cache/requests
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 5088d 22h /openrisc/trunk/or1ksim/autom4te.cache/requests
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 5098d 18h /openrisc/trunk/or1ksim/autom4te.cache/requests
226 Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated julius 5221d 01h /openrisc/trunk/or1ksim/autom4te.cache/requests
202 Adding executed log in binary format capability to or1ksim julius 5234d 04h /openrisc/trunk/or1ksim/autom4te.cache/requests
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5440d 03h /openrisc/trunk/or1ksim/autom4te.cache/requests
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5652d 10h /openrisc/trunk/or1ksim/autom4te.cache/requests

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.