URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [autom4te.cache/] [traces.0] - Rev 450

Rev	Log message	Author	Age	Path
442	OR1Ksim - adding trace controlability by SIGUSR1 signal.	julius	5091d 20h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
436	Or1ksim ethernet TAP updates. Ethernet test still failing.	julius	5101d 16h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
428	or1ksim - adding preliminary PHY emulation to ethernet peripheral.	julius	5111d 21h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
418	Or1ksim - adding new option when configuring memories, "exitnops"	julius	5120d 05h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
233	New softfloat FPU and testfloat sw for or1ksim	julius	5220d 17h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
226	Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated	julius	5223d 23h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
202	Adding executed log in binary format capability to or1ksim	julius	5237d 01h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
60	Mark Jarvin's patches to support Mac OS X (Snow Leopard).	jeremybennett	5443d 01h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
19	Initial commit of Or1ksim 0.3.0 into the new repository	jeremybennett	5655d 08h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0