URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [autom4te.cache/] [traces.0] - Rev 477

Rev	Log message	Author	Age	Path
457	or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again.	julius	5067d 12h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
442	OR1Ksim - adding trace controlability by SIGUSR1 signal.	julius	5084d 06h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
436	Or1ksim ethernet TAP updates. Ethernet test still failing.	julius	5094d 02h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
428	or1ksim - adding preliminary PHY emulation to ethernet peripheral.	julius	5104d 08h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
418	Or1ksim - adding new option when configuring memories, "exitnops"	julius	5112d 15h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
233	New softfloat FPU and testfloat sw for or1ksim	julius	5213d 04h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
226	Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated	julius	5216d 09h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
202	Adding executed log in binary format capability to or1ksim	julius	5229d 12h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
60	Mark Jarvin's patches to support Mac OS X (Snow Leopard).	jeremybennett	5435d 12h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0
19	Initial commit of Or1ksim 0.3.0 into the new repository	jeremybennett	5647d 18h	/openrisc/trunk/or1ksim/autom4te.cache/traces.0