OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [configure.ac] - Rev 793

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
792 Added a MAINTAINERS file.

012-04-07 Jeremy Bennett <jeremy.bennett@embecosm.com>

* MAINTAINERS: Added.
* configure: Regenerated.
* configure.ac: Updated version.
jeremybennett 4617d 00h /openrisc/trunk/or1ksim/configure.ac
787 Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k:

2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>

Patch from R Diez <rdiezmail-openrisc@yahoo.de>

* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
* inst-set-test/inst-set-test.S, int-test/int-test.S,
* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
start-up. There is no guarantee that R0 is hardwired to zero, and
indeed it is not when simulating the or1200 Verilog core.
* configure: Regenerated.
* configure.ac: Updated version.
jeremybennett 4631d 23h /openrisc/trunk/or1ksim/configure.ac
784 Patch from R Diez to ensure DejaGnu handles errors better. Autoconf infrastructure all updated.

2012-03-21 Jeremy Bennett <jeremy.bennett@embecosm.com>

Patch from R Diez <rdiezmail-openrisc@yahoo.de>

* Makefile.am: Add AM_RUNTESTFLAGS to trigger correct error
behaviour.
jeremybennett 4633d 13h /openrisc/trunk/or1ksim/configure.ac
625 Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. jeremybennett 4852d 21h /openrisc/trunk/or1ksim/configure.ac
569 Added AM_SILENT_RULES for nicer builds olof 4890d 17h /openrisc/trunk/or1ksim/configure.ac
556 or1ksim - added performance counters unit and test for it. julius 4922d 13h /openrisc/trunk/or1ksim/configure.ac
552 or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets julius 4923d 22h /openrisc/trunk/or1ksim/configure.ac
538 or1ksim updates. spr-def.h updates, Cygwin compile error fixes. julius 4950d 18h /openrisc/trunk/or1ksim/configure.ac
532 Ensure the halted flag is cleared when the processor is unstalled. jeremybennett 4961d 14h /openrisc/trunk/or1ksim/configure.ac
510 Updates for release 0.5.1rc1. jeremybennett 4981d 22h /openrisc/trunk/or1ksim/configure.ac
508 Updates for Or1ksim 0.5.0rc3. jeremybennett 4982d 22h /openrisc/trunk/or1ksim/configure.ac
494 Change to ensure handles ctrl-C correctly with empty line. jeremybennett 5024d 15h /openrisc/trunk/or1ksim/configure.ac
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 5047d 23h /openrisc/trunk/or1ksim/configure.ac
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 5074d 23h /openrisc/trunk/or1ksim/configure.ac
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 5095d 17h /openrisc/trunk/or1ksim/configure.ac
440 Updated documentation to describe new Ethernet usage. jeremybennett 5102d 13h /openrisc/trunk/or1ksim/configure.ac
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 5114d 14h /openrisc/trunk/or1ksim/configure.ac
432 Updates to handle interrupts correctly. jeremybennett 5115d 17h /openrisc/trunk/or1ksim/configure.ac
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 5129d 18h /openrisc/trunk/or1ksim/configure.ac
387 Fixed testing, to always use our DEJAGNU config. jeremybennett 5169d 18h /openrisc/trunk/or1ksim/configure.ac

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.