OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [common/] [execute.h] - Rev 860

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
552 or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets julius 4902d 20h /openrisc/trunk/or1ksim/cpu/common/execute.h
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 5097d 12h /openrisc/trunk/or1ksim/cpu/common/execute.h
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 5108d 16h /openrisc/trunk/or1ksim/cpu/common/execute.h
202 Adding executed log in binary format capability to or1ksim julius 5225d 16h /openrisc/trunk/or1ksim/cpu/common/execute.h
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5257d 12h /openrisc/trunk/or1ksim/cpu/common/execute.h
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5263d 13h /openrisc/trunk/or1ksim/cpu/common/execute.h
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5643d 22h /openrisc/trunk/or1ksim/cpu/common/execute.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.