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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or1k/] [spr-defs.h] - Rev 695

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561 or1ksim - timer module, spr-defs.h re-bugfix julius 5003d 05h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
559 or1ksim - spr-def.sh fix for timer julius 5004d 17h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
538 or1ksim updates. spr-def.h updates, Cygwin compile error fixes. julius 5037d 03h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 5134d 09h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 5161d 08h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
432 Updates to handle interrupts correctly. jeremybennett 5202d 03h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
239 or1ksim fixed SPR_VR_RESV value julius 5313d 05h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
233 New softfloat FPU and testfloat sw for or1ksim julius 5316d 19h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
226 Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated julius 5320d 00h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5320d 07h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.		 jeremybennett 5421d 00h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5751d 09h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h

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