OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or1k/] [spr-defs.h] - Rev 486

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
486 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 5162d 23h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 5185d 06h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
432 Updates to handle interrupts correctly. jeremybennett 5226d 00h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
239 or1ksim fixed SPR_VR_RESV value julius 5337d 03h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
233 New softfloat FPU and testfloat sw for or1ksim julius 5340d 17h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
226 Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated julius 5343d 22h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5344d 05h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.		 jeremybennett 5444d 22h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5775d 07h /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.