URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or1k/] [sprs.c] - Rev 538

Rev	Log message	Author	Age	Path
508	Updates for Or1ksim 0.5.0rc3.	jeremybennett	4980d 23h	/openrisc/trunk/or1ksim/cpu/or1k/sprs.c
436	Or1ksim ethernet TAP updates. Ethernet test still failing.	julius	5109d 10h	/openrisc/trunk/or1ksim/cpu/or1k/sprs.c
432	Updates to handle interrupts correctly.	jeremybennett	5113d 19h	/openrisc/trunk/or1ksim/cpu/or1k/sprs.c
430	or1ksim - clarifying interrupt behavior in code and documentation.	julius	5116d 16h	/openrisc/trunk/or1ksim/cpu/or1k/sprs.c
226	Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated	julius	5231d 16h	/openrisc/trunk/or1ksim/cpu/or1k/sprs.c
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5303d 19h	/openrisc/trunk/or1ksim/cpu/or1k/sprs.c
19	Initial commit of Or1ksim 0.3.0 into the new repository	jeremybennett	5663d 01h	/openrisc/trunk/or1ksim/cpu/or1k/sprs.c