URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [generate.c] - Rev 146

Rev	Log message	Author	Age	Path
121	Adds exception handling to l.jalr and l.jr. Adds appropriate tests.	jeremybennett	5305d 01h	/openrisc/trunk/or1ksim/cpu/or32/generate.c
118	New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library.	jeremybennett	5305d 22h	/openrisc/trunk/or1ksim/cpu/or32/generate.c
104	Candidate release 0.4.0rc4	jeremybennett	5316d 09h	/openrisc/trunk/or1ksim/cpu/or32/generate.c
100	Single precision FPU stuff for or1ksim	julius	5325d 05h	/openrisc/trunk/or1ksim/cpu/or32/generate.c
96	Various changes which had not been picked up in earlier commits.	jeremybennett	5346d 11h	/openrisc/trunk/or1ksim/cpu/or32/generate.c
82	Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check". Incorporate Mark Jarvis's fixes for Mac OS X.	jeremybennett	5360d 01h	/openrisc/trunk/or1ksim/cpu/or32/generate.c
19	Initial commit of Or1ksim 0.3.0 into the new repository	jeremybennett	5690d 10h	/openrisc/trunk/or1ksim/cpu/or32/generate.c