OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Rev 147

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5264d 21h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
127 New config option to allow l.xori with unsigned operand. jeremybennett 5278d 21h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5279d 17h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5279d 21h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
122 Added l.ror and l.rori with associated tests. jeremybennett 5280d 17h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5280d 17h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5281d 14h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5283d 17h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5284d 17h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5284d 18h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5285d 17h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5288d 18h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
104 Candidate release 0.4.0rc4 jeremybennett 5292d 01h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
100 Single precision FPU stuff for or1ksim julius 5300d 21h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.
jeremybennett 5335d 17h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5666d 02h /openrisc/trunk/or1ksim/cpu/or32/insnset.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.