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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Rev 460

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460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 5071d 07h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
236 Terminate execution on NOP_EXIT, even if debugging, add support for RSP qAttached packet, stall in library after single instruction is ST bit is set in SPR DMR1. Fix softfloat to allow compilation with -O0 for debugging.

* configure: Regenerated.
* configure.ac: Version changed to current date. Test for
varargs.h dropped.
* cpu/or32/insnset.c <l_nop>: Terminate execution on NOP_EXIT,
even if debugging.
* debug/rsp-server.c (rsp_query): Added support for qAttached
packet.
* libtoplevel.c (or1ksim_run): Stall after a single instruction if
SPR_DMR1_ST flag is set.
* softfloat/host.h: Make #define of INLINE conditional, to allow
the user to override.
* softfloat/README: Added instructions for non-optimized compilation.
* softfloat/softfloat-macros: Add a conditional #ifndef
NO_SOFTFLOAT_UNUSUED around unused functions.
jeremybennett 5225d 00h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
235 Removed support for old OpenRISC JTAG Remote Protocol. jeremybennett 5225d 05h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
233 New softfloat FPU and testfloat sw for or1ksim julius 5226d 17h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
226 Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated julius 5229d 23h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
220 Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this. jeremybennett 5236d 22h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5260d 02h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
127 New config option to allow l.xori with unsigned operand. jeremybennett 5274d 02h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5274d 22h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5275d 02h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
122 Added l.ror and l.rori with associated tests. jeremybennett 5275d 22h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5275d 23h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5276d 20h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5278d 23h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5279d 23h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5280d 00h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5280d 22h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5283d 23h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
104 Candidate release 0.4.0rc4 jeremybennett 5287d 06h /openrisc/trunk/or1ksim/cpu/or32/insnset.c
100 Single precision FPU stuff for or1ksim julius 5296d 03h /openrisc/trunk/or1ksim/cpu/or32/insnset.c

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