OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] [or1ksim.info] - Rev 615

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
556 or1ksim - added performance counters unit and test for it. julius 4953d 14h /openrisc/trunk/or1ksim/doc/or1ksim.info
552 or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets julius 4954d 23h /openrisc/trunk/or1ksim/doc/or1ksim.info
538 or1ksim updates. spr-def.h updates, Cygwin compile error fixes. julius 4981d 19h /openrisc/trunk/or1ksim/doc/or1ksim.info
510 Updates for release 0.5.1rc1. jeremybennett 5012d 22h /openrisc/trunk/or1ksim/doc/or1ksim.info
508 Updates for Or1ksim 0.5.0rc3. jeremybennett 5013d 22h /openrisc/trunk/or1ksim/doc/or1ksim.info
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 5079d 00h /openrisc/trunk/or1ksim/doc/or1ksim.info
472 Various changes which improve the quality of the tracing. jeremybennett 5098d 01h /openrisc/trunk/or1ksim/doc/or1ksim.info
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 5105d 23h /openrisc/trunk/or1ksim/doc/or1ksim.info
451 More tidying up. jeremybennett 5126d 14h /openrisc/trunk/or1ksim/doc/or1ksim.info
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 5126d 18h /openrisc/trunk/or1ksim/doc/or1ksim.info
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 5132d 12h /openrisc/trunk/or1ksim/doc/or1ksim.info
440 Updated documentation to describe new Ethernet usage. jeremybennett 5133d 14h /openrisc/trunk/or1ksim/doc/or1ksim.info
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 5142d 09h /openrisc/trunk/or1ksim/doc/or1ksim.info
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 5145d 15h /openrisc/trunk/or1ksim/doc/or1ksim.info
432 Updates to handle interrupts correctly. jeremybennett 5146d 18h /openrisc/trunk/or1ksim/doc/or1ksim.info
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 5149d 14h /openrisc/trunk/or1ksim/doc/or1ksim.info
429 or1ksim update - remove debug printfs from eth MDIO emulation function
and fix illegal instruction vector jump for invalid instructions.		 julius 5149d 18h /openrisc/trunk/or1ksim/doc/or1ksim.info
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 5160d 19h /openrisc/trunk/or1ksim/doc/or1ksim.info
418 Or1ksim - adding new option when configuring memories, "exitnops" julius 5160d 21h /openrisc/trunk/or1ksim/doc/or1ksim.info
385 Updates for Or1ksim 0.5.0rc2.

* configure: Regenerated.
* configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.

* testsuite/test-code-or1k/configure: Regenerated.
* testsuite/test-code-or1k/configure.ac: Handle the case where
target_cpu is not set. Version changed to 0.5.0rc2.
* testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
Definition corrected.		 jeremybennett 5200d 19h /openrisc/trunk/or1ksim/doc/or1ksim.info

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.