| Rev |
Log message |
Author |
Age |
Path |
| 787 |
Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k:
2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>
Patch from R Diez <rdiezmail-openrisc@yahoo.de>
* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
* inst-set-test/inst-set-test.S, int-test/int-test.S,
* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
start-up. There is no guarantee that R0 is hardwired to zero, and
indeed it is not when simulating the or1200 Verilog core.
* configure: Regenerated.
* configure.ac: Updated version. |
jeremybennett |
4632d 02h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 784 |
Patch from R Diez to ensure DejaGnu handles errors better. Autoconf infrastructure all updated.
2012-03-21 Jeremy Bennett <jeremy.bennett@embecosm.com>
Patch from R Diez <rdiezmail-openrisc@yahoo.de>
* Makefile.am: Add AM_RUNTESTFLAGS to trigger correct error
behaviour. |
jeremybennett |
4633d 17h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 625 |
Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. |
jeremybennett |
4853d 00h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 556 |
or1ksim - added performance counters unit and test for it. |
julius |
4922d 17h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 552 |
or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets |
julius |
4924d 01h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 538 |
or1ksim updates. spr-def.h updates, Cygwin compile error fixes. |
julius |
4950d 21h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 510 |
Updates for release 0.5.1rc1. |
jeremybennett |
4982d 01h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 508 |
Updates for Or1ksim 0.5.0rc3. |
jeremybennett |
4983d 01h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 483 |
Updated with new opcodes to generate random numbers and to identify us as Or1ksim. |
jeremybennett |
5048d 03h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 472 |
Various changes which improve the quality of the tracing. |
jeremybennett |
5067d 04h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 460 |
Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. |
jeremybennett |
5075d 02h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 451 |
More tidying up. |
jeremybennett |
5095d 17h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 450 |
Simplified (and hopefully more reliable) Ethernet MAC/PHY. |
jeremybennett |
5095d 20h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 442 |
OR1Ksim - adding trace controlability by SIGUSR1 signal. |
julius |
5101d 15h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 440 |
Updated documentation to describe new Ethernet usage. |
jeremybennett |
5102d 17h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 436 |
Or1ksim ethernet TAP updates. Ethernet test still failing. |
julius |
5111d 11h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 434 |
Work in progress with new Ethernet TUN/TAP interface. |
jeremybennett |
5114d 17h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 432 |
Updates to handle interrupts correctly. |
jeremybennett |
5115d 21h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 430 |
or1ksim - clarifying interrupt behavior in code and documentation. |
julius |
5118d 17h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
| 429 |
or1ksim update - remove debug printfs from eth MDIO emulation function
and fix illegal instruction vector jump for invalid instructions. |
julius |
5118d 21h |
/openrisc/trunk/or1ksim/doc/or1ksim.info |
