OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] [or1ksim.texi] - Rev 107

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
104 Candidate release 0.4.0rc4 jeremybennett 5294d 23h /openrisc/trunk/or1ksim/doc/or1ksim.texi
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5303d 17h /openrisc/trunk/or1ksim/doc/or1ksim.texi
100 Single precision FPU stuff for or1ksim julius 5303d 19h /openrisc/trunk/or1ksim/doc/or1ksim.texi
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5309d 18h /openrisc/trunk/or1ksim/doc/or1ksim.texi
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5330d 16h /openrisc/trunk/or1ksim/doc/or1ksim.texi
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.
jeremybennett 5338d 15h /openrisc/trunk/or1ksim/doc/or1ksim.texi
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5669d 01h /openrisc/trunk/or1ksim/doc/or1ksim.texi

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.