OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] [or1ksim.texi] - Rev 433

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
432 Updates to handle interrupts correctly. jeremybennett 5094d 20h /openrisc/trunk/or1ksim/doc/or1ksim.texi
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 5097d 17h /openrisc/trunk/or1ksim/doc/or1ksim.texi
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 5100d 16h /openrisc/trunk/or1ksim/doc/or1ksim.texi
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 5108d 21h /openrisc/trunk/or1ksim/doc/or1ksim.texi
418 Or1ksim - adding new option when configuring memories, "exitnops" julius 5109d 00h /openrisc/trunk/or1ksim/doc/or1ksim.texi
385 Updates for Or1ksim 0.5.0rc2.

* configure: Regenerated.
* configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.

* testsuite/test-code-or1k/configure: Regenerated.
* testsuite/test-code-or1k/configure.ac: Handle the case where
target_cpu is not set. Version changed to 0.5.0rc2.
* testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
Definition corrected.		 jeremybennett 5148d 22h /openrisc/trunk/or1ksim/doc/or1ksim.texi
346 Changes to support Or1ksim 0.5.0rc1

Top level changes:

* config.h.in: Regenerated.
* debug.cfg, rsp.cfg: Deleted.
* doc/or1ksim.texi: Updated for new options and library interface.
* doc/or1ksim.info, doc/version.texi: Regenerated.
* Makefile.am: Added sim.cfg to EXTRA_DIST.
* NEWS: Updated for 0.5.0rc1.
* or1ksim.h <enum or1ksim_rc>: OR1KSIM_RC_OK explicitly zero.
* sim.cfg: Updated for consistency with the user guide.
* sim-config.c (init_defconfig): 50000 as default VAPI port.
(alloc_memory_block): Verbose message of amount allocated.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.

Changes in testsuite:

* libsim.tests/int-edge.exp <int-edge simple 1>: Increase time
between interrupts to 2ms.
<int-edge simple 2>: Increase time between interrupts to 2ms.
<int-edge duplicated 1>: Increase time between interrupts to 2ms.
<int-edge duplicated 2>: Increase time between interrupts to 2ms.

Changes in testsuite/test-code-or1k:

* mc-common/except-mc.S: Remove leading underscores from global
symbols.
* except/except.S: Remove leading underscores from global symbols.
* cache/cache-asm.S: Remove leading underscores from global symbols.
* cache/cache.c (jump_and_link): Remove leading underscore from
label.
(jump): Remove leading underscore from label.
(all): Remove leading underscore from global symbol references.
* testfloat/systfloat.S: Remove leading underscores from global
symbols.
* mmu/mmu.c (jump): Remove leading underscore from label.
* mmu/mmu-asm.S: Remove leading underscores from global symbols.
* except-test/except-test.c: Remove leading underscores from
global symbols.
* except-test/except-test-s.S: Remove leading underscores from
global symbols.
* uos/except-or32.S: Remove leading underscores from global
symbols.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.		 jeremybennett 5174d 00h /openrisc/trunk/or1ksim/doc/or1ksim.texi
235 Removed support for old OpenRISC JTAG Remote Protocol. jeremybennett 5208d 00h /openrisc/trunk/or1ksim/doc/or1ksim.texi
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5213d 01h /openrisc/trunk/or1ksim/doc/or1ksim.texi
202 Adding executed log in binary format capability to or1ksim julius 5225d 21h /openrisc/trunk/or1ksim/doc/or1ksim.texi
127 New config option to allow l.xori with unsigned operand. jeremybennett 5256d 22h /openrisc/trunk/or1ksim/doc/or1ksim.texi
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5257d 17h /openrisc/trunk/or1ksim/doc/or1ksim.texi
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5263d 17h /openrisc/trunk/or1ksim/doc/or1ksim.texi
104 Candidate release 0.4.0rc4 jeremybennett 5270d 02h /openrisc/trunk/or1ksim/doc/or1ksim.texi
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5278d 19h /openrisc/trunk/or1ksim/doc/or1ksim.texi
100 Single precision FPU stuff for or1ksim julius 5278d 22h /openrisc/trunk/or1ksim/doc/or1ksim.texi
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5284d 21h /openrisc/trunk/or1ksim/doc/or1ksim.texi
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5305d 19h /openrisc/trunk/or1ksim/doc/or1ksim.texi
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.		 jeremybennett 5313d 18h /openrisc/trunk/or1ksim/doc/or1ksim.texi
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5644d 03h /openrisc/trunk/or1ksim/doc/or1ksim.texi

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.