| Rev |
Log message |
Author |
Age |
Path |
| 787 |
Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k:
2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>
Patch from R Diez <rdiezmail-openrisc@yahoo.de>
* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
* inst-set-test/inst-set-test.S, int-test/int-test.S,
* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
start-up. There is no guarantee that R0 is hardwired to zero, and
indeed it is not when simulating the or1200 Verilog core.
* configure: Regenerated.
* configure.ac: Updated version. |
jeremybennett |
4661d 16h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 784 |
Patch from R Diez to ensure DejaGnu handles errors better. Autoconf infrastructure all updated.
2012-03-21 Jeremy Bennett <jeremy.bennett@embecosm.com>
Patch from R Diez <rdiezmail-openrisc@yahoo.de>
* Makefile.am: Add AM_RUNTESTFLAGS to trigger correct error
behaviour. |
jeremybennett |
4663d 07h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 625 |
Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. |
jeremybennett |
4882d 14h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 561 |
or1ksim - timer module, spr-defs.h re-bugfix |
julius |
4946d 13h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 556 |
or1ksim - added performance counters unit and test for it. |
julius |
4952d 07h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 552 |
or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets |
julius |
4953d 15h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 538 |
or1ksim updates. spr-def.h updates, Cygwin compile error fixes. |
julius |
4980d 11h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 510 |
Updates for release 0.5.1rc1. |
jeremybennett |
5011d 15h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 494 |
Change to ensure handles ctrl-C correctly with empty line. |
jeremybennett |
5054d 08h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 460 |
Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. |
jeremybennett |
5104d 16h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 451 |
More tidying up. |
jeremybennett |
5125d 06h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 450 |
Simplified (and hopefully more reliable) Ethernet MAC/PHY. |
jeremybennett |
5125d 10h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 442 |
OR1Ksim - adding trace controlability by SIGUSR1 signal. |
julius |
5131d 05h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 440 |
Updated documentation to describe new Ethernet usage. |
jeremybennett |
5132d 06h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 434 |
Work in progress with new Ethernet TUN/TAP interface. |
jeremybennett |
5144d 07h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 432 |
Updates to handle interrupts correctly. |
jeremybennett |
5145d 10h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 430 |
or1ksim - clarifying interrupt behavior in code and documentation. |
julius |
5148d 07h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 428 |
or1ksim - adding preliminary PHY emulation to ethernet peripheral. |
julius |
5151d 06h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 420 |
New feature to trace instructions (option --trace). Manual updated to match. |
jeremybennett |
5159d 11h |
/openrisc/trunk/or1ksim/doc/version.texi |
| 418 |
Or1ksim - adding new option when configuring memories, "exitnops" |
julius |
5159d 14h |
/openrisc/trunk/or1ksim/doc/version.texi |
