OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [peripheral/] [eth.c] - Rev 461

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 5072d 22h /openrisc/trunk/or1ksim/peripheral/eth.c
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 5082d 17h /openrisc/trunk/or1ksim/peripheral/eth.c
451 More tidying up. jeremybennett 5093d 13h /openrisc/trunk/or1ksim/peripheral/eth.c
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 5093d 17h /openrisc/trunk/or1ksim/peripheral/eth.c
443 Work in progress on more efficient Ethernet. jeremybennett 5098d 21h /openrisc/trunk/or1ksim/peripheral/eth.c
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 5099d 11h /openrisc/trunk/or1ksim/peripheral/eth.c
437 Or1ksim - ethernet peripheral update, working much better. julius 5108d 07h /openrisc/trunk/or1ksim/peripheral/eth.c
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 5109d 07h /openrisc/trunk/or1ksim/peripheral/eth.c
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 5112d 14h /openrisc/trunk/or1ksim/peripheral/eth.c
429 or1ksim update - remove debug printfs from eth MDIO emulation function
and fix illegal instruction vector jump for invalid instructions.
julius 5116d 17h /openrisc/trunk/or1ksim/peripheral/eth.c
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 5119d 13h /openrisc/trunk/or1ksim/peripheral/eth.c
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5231d 22h /openrisc/trunk/or1ksim/peripheral/eth.c
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.
jeremybennett 5332d 14h /openrisc/trunk/or1ksim/peripheral/eth.c
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5662d 23h /openrisc/trunk/or1ksim/peripheral/eth.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.