URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [peripheral/] [mc-defines.h] - Rev 465

Rev	Log message	Author	Age	Path
385	Updates for Or1ksim 0.5.0rc2. * configure: Regenerated. * configure.ac: Minor tidy ups. Version changed to 0.5.0rc2. * debug/rsp-server.c (rsp_query): Simplified handling of "qTStatus" to indicate we just do not support tracing. * doc/or1ksim.texi <Configuring the Build>: No longer mandatory to specify the target. <Memory Configuration>: Warns about issues with memory controller. <Memory Controller Configuration>: Warns about issues with memory controller and advises not to use it. <Standalone Simulator>: Details for options with arguments updated. * NEWS: Updated for 0.5.0rc2. * peripheral/mc.c (mc_poc): Use constant MC_POC_VALID (mc_index): Ensure value is valid. * peripheral/mc-defines.h <MC_CE_VALID>: Defined. * testsuite/test-code-or1k/configure: Regenerated. * testsuite/test-code-or1k/configure.ac: Handle the case where target_cpu is not set. Version changed to 0.5.0rc2. * testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>: Definition corrected.	jeremybennett	5146d 17h	/openrisc/trunk/or1ksim/peripheral/mc-defines.h
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5261d 13h	/openrisc/trunk/or1ksim/peripheral/mc-defines.h
110	or1ksim make check should work without a libc in the or32-elf tools	julius	5262d 14h	/openrisc/trunk/or1ksim/peripheral/mc_defines.h