OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [peripheral/] [mc.c] - Rev 379

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5221d 14h /openrisc/trunk/or1ksim/peripheral/mc.c
104 Candidate release 0.4.0rc4 jeremybennett 5278d 14h /openrisc/trunk/or1ksim/peripheral/mc.c
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5293d 09h /openrisc/trunk/or1ksim/peripheral/mc.c
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.
jeremybennett 5322d 06h /openrisc/trunk/or1ksim/peripheral/mc.c
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5652d 15h /openrisc/trunk/or1ksim/peripheral/mc.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.