URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [sim-config.h] - Rev 220

Rev	Log message	Author	Age	Path
220	Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this.	jeremybennett	5236d 20h	/openrisc/trunk/or1ksim/sim-config.h
202	Adding executed log in binary format capability to or1ksim	julius	5243d 00h	/openrisc/trunk/or1ksim/sim-config.h
143	Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195).	jeremybennett	5260d 01h	/openrisc/trunk/or1ksim/sim-config.h
100	Single precision FPU stuff for or1ksim	julius	5296d 01h	/openrisc/trunk/or1ksim/sim-config.h
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5302d 00h	/openrisc/trunk/or1ksim/sim-config.h
93	Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0.	jeremybennett	5322d 22h	/openrisc/trunk/or1ksim/sim-config.h
82	Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check". Incorporate Mark Jarvis's fixes for Mac OS X.	jeremybennett	5330d 21h	/openrisc/trunk/or1ksim/sim-config.h
19	Initial commit of Or1ksim 0.3.0 into the new repository	jeremybennett	5661d 07h	/openrisc/trunk/or1ksim/sim-config.h