OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [ChangeLog] - Rev 821

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
797 testsuite: kill test processes that timeout pgavin 4584d 17h /openrisc/trunk/or1ksim/testsuite/ChangeLog
784 Patch from R Diez to ensure DejaGnu handles errors better. Autoconf infrastructure all updated.

2012-03-21 Jeremy Bennett <jeremy.bennett@embecosm.com>

Patch from R Diez <rdiezmail-openrisc@yahoo.de>

* Makefile.am: Add AM_RUNTESTFLAGS to trigger correct error
behaviour.		 jeremybennett 4621d 10h /openrisc/trunk/or1ksim/testsuite/ChangeLog
625 Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. jeremybennett 4840d 17h /openrisc/trunk/or1ksim/testsuite/ChangeLog
556 or1ksim - added performance counters unit and test for it. julius 4910d 10h /openrisc/trunk/or1ksim/testsuite/ChangeLog
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 5062d 19h /openrisc/trunk/or1ksim/testsuite/ChangeLog
458 or1ksim testsuite updates julius 5063d 23h /openrisc/trunk/or1ksim/testsuite/ChangeLog
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 5072d 14h /openrisc/trunk/or1ksim/testsuite/ChangeLog
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 5102d 10h /openrisc/trunk/or1ksim/testsuite/ChangeLog
432 Updates to handle interrupts correctly. jeremybennett 5103d 14h /openrisc/trunk/or1ksim/testsuite/ChangeLog
346 Changes to support Or1ksim 0.5.0rc1

Top level changes:

* config.h.in: Regenerated.
* debug.cfg, rsp.cfg: Deleted.
* doc/or1ksim.texi: Updated for new options and library interface.
* doc/or1ksim.info, doc/version.texi: Regenerated.
* Makefile.am: Added sim.cfg to EXTRA_DIST.
* NEWS: Updated for 0.5.0rc1.
* or1ksim.h <enum or1ksim_rc>: OR1KSIM_RC_OK explicitly zero.
* sim.cfg: Updated for consistency with the user guide.
* sim-config.c (init_defconfig): 50000 as default VAPI port.
(alloc_memory_block): Verbose message of amount allocated.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.

Changes in testsuite:

* libsim.tests/int-edge.exp <int-edge simple 1>: Increase time
between interrupts to 2ms.
<int-edge simple 2>: Increase time between interrupts to 2ms.
<int-edge duplicated 1>: Increase time between interrupts to 2ms.
<int-edge duplicated 2>: Increase time between interrupts to 2ms.

Changes in testsuite/test-code-or1k:

* mc-common/except-mc.S: Remove leading underscores from global
symbols.
* except/except.S: Remove leading underscores from global symbols.
* cache/cache-asm.S: Remove leading underscores from global symbols.
* cache/cache.c (jump_and_link): Remove leading underscore from
label.
(jump): Remove leading underscore from label.
(all): Remove leading underscore from global symbol references.
* testfloat/systfloat.S: Remove leading underscores from global
symbols.
* mmu/mmu.c (jump): Remove leading underscore from label.
* mmu/mmu-asm.S: Remove leading underscores from global symbols.
* except-test/except-test.c: Remove leading underscores from
global symbols.
* except-test/except-test-s.S: Remove leading underscores from
global symbols.
* uos/except-or32.S: Remove leading underscores from global
symbols.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.		 jeremybennett 5182d 17h /openrisc/trunk/or1ksim/testsuite/ChangeLog
235 Removed support for old OpenRISC JTAG Remote Protocol. jeremybennett 5216d 17h /openrisc/trunk/or1ksim/testsuite/ChangeLog
234 Minor tidy ups. DOS end of line chars fixed. jeremybennett 5217d 19h /openrisc/trunk/or1ksim/testsuite/ChangeLog
220 Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this. jeremybennett 5228d 10h /openrisc/trunk/or1ksim/testsuite/ChangeLog
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5266d 10h /openrisc/trunk/or1ksim/testsuite/ChangeLog
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5266d 14h /openrisc/trunk/or1ksim/testsuite/ChangeLog
122 Added l.ror and l.rori with associated tests. jeremybennett 5267d 10h /openrisc/trunk/or1ksim/testsuite/ChangeLog
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5267d 11h /openrisc/trunk/or1ksim/testsuite/ChangeLog
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5268d 08h /openrisc/trunk/or1ksim/testsuite/ChangeLog
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5270d 11h /openrisc/trunk/or1ksim/testsuite/ChangeLog
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5271d 11h /openrisc/trunk/or1ksim/testsuite/ChangeLog

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.