OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [README] - Rev 311

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
234 Minor tidy ups. DOS end of line chars fixed. jeremybennett 5217d 22h /openrisc/trunk/or1ksim/testsuite/README
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5266d 14h /openrisc/trunk/or1ksim/testsuite/README
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5266d 18h /openrisc/trunk/or1ksim/testsuite/README
122 Added l.ror and l.rori with associated tests. jeremybennett 5267d 14h /openrisc/trunk/or1ksim/testsuite/README
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5267d 15h /openrisc/trunk/or1ksim/testsuite/README
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5268d 11h /openrisc/trunk/or1ksim/testsuite/README
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5270d 15h /openrisc/trunk/or1ksim/testsuite/README
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5271d 14h /openrisc/trunk/or1ksim/testsuite/README
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5271d 15h /openrisc/trunk/or1ksim/testsuite/README
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5272d 14h /openrisc/trunk/or1ksim/testsuite/README
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5275d 15h /openrisc/trunk/or1ksim/testsuite/README
104 Candidate release 0.4.0rc4 jeremybennett 5278d 22h /openrisc/trunk/or1ksim/testsuite/README
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5293d 17h /openrisc/trunk/or1ksim/testsuite/README
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5307d 23h /openrisc/trunk/or1ksim/testsuite/README
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5314d 15h /openrisc/trunk/or1ksim/testsuite/README
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5321d 15h /openrisc/trunk/or1ksim/testsuite/README
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.
jeremybennett 5322d 14h /openrisc/trunk/or1ksim/testsuite/README

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.