URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [libsim.tests/] [Makefile.am] - Rev 243

Rev	Log message	Author	Age	Path
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5312d 22h	/openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.am
97	Updates to test the new JTAG library interface (not yet complete).	jeremybennett	5327d 04h	/openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.am
93	Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0.	jeremybennett	5333d 19h	/openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.am
90	Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain).	jeremybennett	5340d 19h	/openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.am