URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [libsim.tests/] [default.cfg] - Rev 496

Rev	Log message	Author	Age	Path
458	or1ksim testsuite updates	julius	5105d 23h	/openrisc/trunk/or1ksim/testsuite/libsim.tests/default.cfg
434	Work in progress with new Ethernet TUN/TAP interface.	jeremybennett	5144d 10h	/openrisc/trunk/or1ksim/testsuite/libsim.tests/default.cfg
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5335d 14h	/openrisc/trunk/or1ksim/testsuite/libsim.tests/default.cfg
90	Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain).	jeremybennett	5363d 11h	/openrisc/trunk/or1ksim/testsuite/libsim.tests/default.cfg